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1 datasheet precision digital power monitor isl28022 the isl28022 is a bidirectional high-side and low-side digital current sense and voltage monito r with serial interface. the device monitors current and voltage and provides the results digitally along with calculated power. the isl28022 provides tight accuracy of less than 0.3% for both voltage and current monitoring over the entire input range. the digital power monitor has configurable faul t thresholds and measurable adc gain ranges. the isl28022 handles common mode input voltage ranging from 0v to 60v. the wide range permits the device to handle telecom, automotive and industri al applications with minimal external circuitry. both high and low-side ground sensing applications are easily handled with the flexible architecture. the isl28022 consumes an averag e current of just 700a and is available in a 10 ld msop packag e. the isl28022 is also offered in a space saving 16 ld qfn pa ckage. the part operates across the extended temperature range from -40c to +125c. related literature ? an1955 , ?design ideas for intersil digital power monitors? ? an1875 , ?isl28022 digital power monitor evaluation kit (isl28022evkit1z) ? an1811 , ?isl28022 digital power monitor 8 site evaluation kit? features ? bus voltage sense range . . . . . . . . . . . . . . . . . . . . . . 0v to 60v ?16-bit ? adc monitors current and voltage ? voltage measuring error . . . . . . . . . . . . . . . . . . . . . . . . . <0.3% ? current measuring error . . . . . . . . . . . . . . . . . . . . . . . . . <0.3% ? handles negative system voltage ? overvoltage/undervoltage an d current fault monitoring ?i 2 c/smbus interface ?wide v cc range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3v to 5.5v ? esd (hbm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8kv ? supports high speed i 2 c . . . . . . . . . . . . . . . . . . . . . . . 3.4mhz applications ?routers and servers ? dc/dc, ac/dc converters ? battery management/charging ? automotive power ?power distribution ? medical and test equipment i 2 c smbus a1 smbclk/scl smbdat/sda vinp vinm gnd rsh adc 16-bit sw mux to c voltage regulator vout en eclk/int v in = 0v to 60v reg map vcc load vbus a0 v cc figure 1. typical application october 2, 2015 fn8386.7 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2013-2015. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl28022 2 fn8386.7 october 2, 2015 submit document feedback table of contents block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 typical performance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 protocol conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 smbus support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 broadcast addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 i 2 c clock speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 signal integrity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 measurement stability vs acquisition time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 fast transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 external clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 over-ranging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 shunt resistor selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 lossless current sensing (dcr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 a trace as a sense resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 m10.118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 l16.3x3b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
isl28022 3 fn8386.7 october 2, 2015 submit document feedback block diagram digital control logic i 2 c sm bus a0 16 a1 smbclk smbdat osc vinm vinp vcc gnd adc 16-bit reg map ref clock div sw mux cm = 0 to 60v eclk/int vbus figure 2. block diagram ordering information part number ( notes 1 , 2 , 3 ) part marking temp range (c) package (rohs compliant) pkg. dwg. # isl28022fuz 8022f -40 to +125 10 ld msop m10.118 isl28022frz 022f -40 to +125 16 ld qfn l16.3x3b isl28022evkit1z isl28022 evaluation kit (includes dongle board, generic evaluation board, r load board) ISL28022MBEV1Z isl28022 generic evaluation board isl28022ev1z isl28022 8-site evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl28022 . for more information on msl please see tech brief tb363 .
isl28022 4 fn8386.7 october 2, 2015 submit document feedback pin configurations isl28022 (10 ld msop) top view isl28022 (16 ld qfn) top view a1 a0 ext_clk/int sda/smbdat scl/smbclk 1 2 3 4 5 10 9 8 7 6 vcc gnd vbus vinm vinp 1 3 4 15 a1 a0 ext_clk/int sda/smbdat nc nc nc vinp 16 14 13 2 12 10 9 11 6 578 vinm vbus gnd vcc scl/smbclk nc nc nc gnd pin descriptions msop pin number qfn pin number pin name description 11 a1i 2 c address, bit1 22 a0i 2 c address, bit0 3 3 ext_clk/int external adc clock input or cpu interrupt output signal. when the pin is configured as an interrupt, the output is an open-drain. 4 4 sda/smbdat i 2 c serial data input/output. 5 5 scl/smbclk i 2 c clock input 6 9 vcc positive power pin. the positive power supply to the part. 7 10 gnd negative power pin. can be connect ed to ground or a negative voltage. 8 11 vbus vbus power voltage sense. 9 12 vinm current sense minus input. 10 13 vinp current sense plus input. 6, 7, 8, 14, 15, 16 nc no connect. no internal connection. epad gnd negative power pin. can be connect ed to ground or a negative voltage.
isl28022 5 fn8386.7 october 2, 2015 submit document feedback table 1. dpm portfolio comparison - isl28022 vs isl28023 vs isl28025 description basic digital power monitor full feature digital power monitor digital power monitor in tiny package part number isl28022 isl28023 isl28025 package msop10, qfn16 qfn24 wlcsp-16 temperature range -40c to +125c -40c to +125c -40c to +125c 0v to 60v input range 0v to 60v opt 1: 0v to 60v opt 2: 0v to 16v opt 1: 0v to 60v opt 2: 0v to 16v adc 16-bit 16-bit 16-bit +25c gain error 0.30% 0.25% 0.25% current measure lsb step 10v 2.5v 2.5v +25c offset 75v 30v 30v primary differential shunt input x x x channel independent bus voltage x x x lv aux differential shunt input x channel independent bus voltage x x vbus lsb step low voltage bus 0.25mv 0.25mv high voltage bus 4mv 1mv/0.25mv 1mv/0.25mv external temperature sensor input x hv internal regulator (3.3v out )xx fast oc/ov/uv alert outputs 2 outputs 2 outputs margin dac x internal temperature sensor x x user select conversion mode/sample rate x x x peak min/max current registers x x slave address locations 16 addresses 55 addresses 55 addresses i 2 c level translators xx pmbus xx i 2 c/smbus x x x high speed (3.4mhz) i 2 c mode x x x external clock input x x x power shutdown mode x x x
isl28022 6 fn8386.7 october 2, 2015 submit document feedback absolute maximum rating s thermal information vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.0v vbus voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..63v common mode input voltage (vinp , vinm) . . . . . . . . . . . . . . . . . . . . . . 63v differential input voltage (vinp, vinm) . . . . . . . . . . . . . . . . . . . . . . . . .63v input voltage (digital pins) . . . . . . . . . . . . . . . . . . . . . . . .gnd - 0.3v to 5.5v output voltage (digital pins) . . . . . . . . . . . . . . . . . . gnd - 0.3 to vcc + 0.3v open-drain output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ma open-drain voltage (interrupt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24v esd rating human body model (tested per jesd22-a114) . . . . . . . . . . . . . . . . . 8kv machine model (tested per jesd22-a115). . . . . . . . . . . . . . . . . . . . 400v charged device model (tested per jesd22-c101). . . . . . . . . . . . . . . 2kv latch-up (tested per jesd-78b) . . . . . . . . . . . . . . . . . . . . . . 60v at +125c thermal resistance (typical) ? ja (c/w) ? jc (c/w) 16 ld qfn ( notes 4 , 5 ) . . . . . . . . . . . . . . . . 52 6.5 10 ld msop ( notes 6 , 7 ) . . . . . . . . . . . . . . . 150 55 maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c maximum junction temperature (t jmax ) . . . . . . . . . . . . . . . . . . . . .+150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions ambient temperature range (t a ) . . . . . . . . . . . . . . . . . . .-40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 6. ? ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 7. for ? j c , the ?case temp? location is taken at the package top center. electrical specifications t a = +25c, v cc = 3.3, vinp = v bus = 12v, v sense = vinp-vinm = 32mv, unless otherwise specified. all voltages with respect to gnd pin. parameter description test conditions min ( note 8 )typ max ( note 8 )unit inputs v sensediff useful full-scale current sense differential voltage range (vinp-vinm) pga gain = /1 0 40 mv pga gain = /2 0 80 mv pga gain = /4 0 160 mv pga gain = /8 0 320 mv v shunt _step lsb step size, shunt voltage 10 v v cmsense current sense common mode (vinp, vinm) 060v v os v sense offset voltage pga gain = /1, /2, /4, /8; adc setting = 1111 10 75 v v ostc v sense offset voltage temperature coefficient 0.15 v/c cmrr v sense v os vs common mode v bus = 0v to 60v; brng = 2, 3 110 130 db psrr v sense v os vs power supply v cc = 3v to 5v 105 db a cs current sense gain error 40 m% a cstc current sense gain error temperature coefficient 1 m%/c i vinact input leakage, vin pins active mode (for both vinp and vinm pins) 20 a i vinact input leakage, vin pins power-down mode (for both vinp and vinm pins) 0.1 0.5 a v bus useful bus voltage range brng = 0 0 16 v brng = 1 0 32 v brng = 2, 3 0 60 v v bus _step lsb step size, bus voltage brng = 0 4 mv v bus _ vco v bus voltage coefficient 50 ppm/v r vbact input impedance, vbus pin active mode 600 k
isl28022 7 fn8386.7 october 2, 2015 submit document feedback dc accuracy adc resolution (native) pga gain = /1, v sense = 320mv 16 bits current measurement error t a = +25c 0.2 0.3 % current measurement error over-temperature t a = -40c to +85c 0.5 % t a = -40c to +125c 1 % bus voltage measurement error t a = +25c 0.2 0.3 % bus voltage measurement error over-temperature t a = -40c to +85c 0.5 % t a = -40c to +125c 1 % adc timing specs t s adc conversion time mode = 5 or 6 adc setting = 0000 72 79.2 s adc setting = 0001 132 145.2 s adc setting = 0010 258 283.8 s adc setting = 0011 508 558.8 s adc setting = 1001 1.01 1.11 ms adc setting = 1010 2.01 2.21 ms adc setting = 1011 4.01 4.41 ms adc setting = 1100 8.01 8.81 ms adc setting = 1101 16.01 17.61 ms adc setting = 1110 32.01 35.21 ms adc setting = 1111 64.01 70.41 ms i 2 c interface specifications v il sda and scl input buffer low voltage -0.3 0.3 x v cc v v ih sda and scl input buffer high voltage 0.7 x v cc v cc + 0.3 v hysteresis sda and scl input buffer hysteresis 0.05 x v cc v v ol sda output buffer low voltage, sinking 3ma v cc = 5v, i ol = 3ma 0 0.02 0.4 v c pin sda and scl pin capacitance t a = +25c, f = 1mhz, v cc = 5v, v in = 0v, v out = 0v 10 pf f scl scl frequency 400 khz t in pulse width suppression time at sda and scl inputs any pulse narrower than the max spec is suppressed. 50 ns t aa scl falling edge to sda output data valid scl falling edge crossing 30% of v cc , until sda exits the 30% to 70% of v cc window. 900 ns t buf time the bus must be free before the start of a new transmission sda crossing 70% of v cc during a stop condition, to sda crossing 70% of v cc during the following start condition. 1300 ns t low clock low time measured at the 30% of v cc crossing. 1300 ns t high clock high time measured at the 70% of v cc crossing. 600 ns t su:sta start condition setup time scl risi ng edge to sda falling edge. both crossing 70% of v cc . 600 ns t hd:sta start condition hold time from sda falling edge crossing 30% of v cc to scl falling edge crossing 70% of v cc . 600 ns electrical specifications t a = +25c, v cc = 3.3, vinp = v bus = 12v, v sense = vinp-vinm = 32mv, unless otherwise specified. all voltages with respect to gnd pin. (continued) parameter description test conditions min ( note 8 )typ max ( note 8 )unit
isl28022 8 fn8386.7 october 2, 2015 submit document feedback t su:dat input data setup time from sda exiting the 30% to 70% of v cc window, to scl rising edge crossing 30% of v cc. 100 ns t hd:dat input data hold time from scl falling edge crossing 30% of v cc to sda entering the 30% to 70% of v cc window. 20 900 ns t su:sto stop condition setup time from scl rising edge crossing 70% of v cc , to sda rising edge crossing 30% of v cc . 600 ns t hd:sto stop condition hold time from sda rising edge to scl falling edge. both crossing 70% of v cc . 600 ns t dh output data hold time from scl falling edge crossing 30% of v cc , until sda enters the 30% to 70% of v cc window. 0ns t r sda and scl rise time from 30% to 70% of v cc 20 + 0.1 x cb 300 ns t f sda and scl fall time from 70% to 30% of v cc 20 + 0.1 x cb 300 ns cb capacitive loading of sda or scl total on-chip and off-chip 75 pf r pu sda and scl bus pull-up resistor off-chip maximum is determined by t r and t f . for cb = 400pf, max is about 2k ~2.5k . for cb = 40pf, max is about 15k ~20k 1k power supply operating supply voltage range 3 5.5 v i ccext power supply current on v cc pin, active mode external power supply mode, v cc = 5v 0.7 1.0 ma i ccpd power supply current on v cc pin, power-down mode external power supply mode, v cc = 5v 515a note: 8. parameters with min and/or ma x limits are 100% tested at +25c, unless otherw ise specified. temperature limits established by characterization and are not production tested. electrical specifications t a = +25c, v cc = 3.3, vinp = v bus = 12v, v sense = vinp-vinm = 32mv, unless otherwise specified. all voltages with respect to gnd pin. (continued) parameter description test conditions min ( note 8 )typ max ( note 8 )unit
isl28022 9 fn8386.7 october 2, 2015 submit document feedback typical performance curves t a = +25c, v cc = 3.3v, vinp = v bus = 12v, s(b)adc = 15; unless otherwise specified. figure 3. v shunt v os figure 4. v shunt v os vs temperature figure 5. v shunt measurement error figure 6. v shunt measurement error vs v shunt input figure 7. v shunt gain vs temperature figure 8. v bus measurement error distribution 0 5 10 15 20 25 -75 -60 -45 -30 -15 0 15 30 45 60 75 hits v shunt v os (v) -0.0750 -0.0625 -0.0500 -0.0375 -0.0250 -0.0125 0 0.0125 0.0250 0.0375 0.0500 0.0625 0.0750 -50 -25 0 25 50 75 100 125 temperature (c) v os (mv) v cc = 3.3v v cc = 3v v cc = 5v sadc = 15 0 5 10 15 20 25 30 35 40 -0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 0.25 0.30 hits v shunt measurement error (%) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 -0.30 -0.25 -0.20 -0.15 -0.10 -0 .05 0 0.05 0.10 0.15 0.20 0.25 0.30 v shunt (v) v shunt measurement error (%) v cc = 5.5v v cc = 3.3v v cc = 3v t = +25c v shunt (cmv) = 12v sadc = 15 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -50 -25 0 25 50 75 100 125 temperature (c) gain error (%) v cc = 5.5v v cc = 3.3v v cc = 3v v shunt (diff) = 32mv v shunt (cmv) = 12v sadc = 15 0 10 20 30 40 50 60 70 -0.30 -0.25 -0.20 -0.15 -0.10 -0 .05 0 0.05 0.10 0.15 0.20 0.25 0.30 hits v bus measurement error (%)
isl28022 10 fn8386.7 october 2, 2015 submit document feedback figure 9. v bus measurement error vs v bus (t a = +25c) figure 10. v bus measurement error vs temperature figure 11. cmrr vs temperature figure 12. supply current vs mode vs temperature figure 13. supply current vs mode vs v cc figure 14. supply current vs mode 0 vs temperature typical performance curves t a = +25c, v cc = 3.3v, vinp = v bus = 12v, s(b)adc = 15; unless otherwise specified. (continued) -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 8 16 24 32 40 48 56 64 v bus (v) v bus measurement error (%) v cc = 5.5v v cc = 3.3v v cc = 3v -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -50 -25 0 25 50 75 100 125 temperature (c) v bus measurement error (%) v cc = 5.5v v cc = 3.3v v cc = 3v 120 125 130 135 140 145 150 155 -50 -25 0 25 50 75 100 125 temperature (c) v cc = 3v v cc = 3.3v v cc = 5v v shunt (dcmv) = 0v to 60v sadc = 15 cmrr (db) 300 350 400 450 500 550 600 650 700 750 800 -50 -25 0 25 50 75 100 125 temperature (c) supply current (a) mode = 7 mode = 4 300 350 400 450 500 550 600 650 700 750 800 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v cc (v) supply current (a) mode = 7 mode = 4 0 2 4 6 8 10 12 14 16 18 20 -50 -25 0 25 50 75 100 125 temperature (c) supply current (a)
isl28022 11 fn8386.7 october 2, 2015 submit document feedback figure 15. supply curr ent vs mode 0 vs v cc figure 16. shunt i vin vs temperature (mode 5) figure 17. shunt i vin vs common mode voltage (mode 5) figure 18. shunt i vin vs temperature (mode 0, 4) figure 19. shunt i vin vs common mode voltage (mode 0, 4) figure 20. shunt i os vs temperature (mode 5) typical performance curves t a = +25c, v cc = 3.3v, vinp = v bus = 12v, s(b)adc = 15; unless otherwise specified. (continued) 0 2 4 6 8 10 12 14 16 18 20 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v cc (v) supply current (a) 5 7 9 11 13 15 17 19 -50 -25 0 25 50 75 100 125 temperature (c) i vin (a) 5 6 7 8 9 10 11 12 13 14 15 0 8 16 24 32 40 48 56 64 v cm (v) i vin (a) 0 0.005 0.010 0.015 0.020 -50 -25 0 25 50 75 100 125 temperature (c) i vin (a) mode = 4 mode = 0 0 0.005 0.010 0.015 0.020 0 8 16 24 32 40 48 56 64 v cm (v) mode = 0 mode = 4 i vin (a) -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -50 -25 0 25 50 75 100 125 temperature (c) i os (a)
isl28022 12 fn8386.7 october 2, 2015 submit document feedback figure 21. shunt i os vs common mode voltage (mode 5) figure 22. shunt i os vs temperature (mode 0, 4) figure 23. shunt i os vs common mode voltage (mode 0, 4) figure 24. v shunt bandwidth vs sadc mode figure 25. v shunt bandwidth vs external clock frequency figure 26. interrupt timing typical performance curves t a = +25c, v cc = 3.3v, vinp = v bus = 12v, s(b)adc = 15; unless otherwise specified. (continued) -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 8 16 24 32 40 48 56 64 v cm (v) i os (a) -0.0020 -0.0015 -0.0010 -0.0005 0 0.0005 0.0010 0.0015 0.0020 -50 -25 0 25 50 75 100 125 temperature (c) i os (a) mode = 4 mode = 0 -0.0020 -0.0015 -0.0010 -0.0005 0 0.0005 0.0010 0.0015 0.0020 0 8 16 24 32 40 48 56 64 v cm (v) i os (a) mode = 4 mode = 0 -50 -40 -30 -20 -10 0 10 10 100 1k 10k frequency (hz) gain (db) sadc = 1 sadc = 0 sadc = 2 sadc = 3 v in = 200mv p-p sine wave -50 -40 -30 -20 -10 0 10 10 100 1k 10k frequency (hz) sadc = 3 f_extclk = off sadc = 3 f_extclk = 768khz sadc = 3 f_extclk = 384khz v in = 200mv p-p sine wave gain (db) -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 time (ms) s(b)adc = 508s s(b)adc = 256s s(b)adc = 72s s(b)adc = 132s mode = 5 or 6 input signal
isl28022 13 fn8386.7 october 2, 2015 submit document feedback functional description overview the isl28022 is a digital power monitor (dpm) device that is capable of measuring bidirectiona l currents while monitoring the bus voltage. the dpm requires an external sh unt resistor to enable current measurements. the shunt resistor translates the bus current to a voltage. the dpm measures the voltage across the shunt resistors and reports the measured value out digitally via an i 2 c interface. a register within the dpm is reserved to store the value of the shunt resistor. the stored current sense resistor value allows the dpm to output the curr ent value to an external digital device. the isl28022 measures bus voltage and current sequentially. the device has a power measurement functionality that multiplies current and voltage measured values. the power calculation is stored in a unique register. the power measurement allows the user to monitor power to or from the load in addition to current and voltage. the isl28022 can monitor supplies from 0v to 60v while operating on a chip supply ranging from 3v to 5.5v. the isl28022 adc sample rate can be configured to an internal oscillator (500khz) or a user can provide a synchronized clock. detailed description the isl28022 consists of a tw o channel analog front end multiplexer, a 16-bit sigma delta adc and digital signal processing/serial communication circuitry. the main block within the device is a 3rd order sigma delta adc. the input signal bandwidth is 1khz, wide enough for power monitoring applications. the main block includes an internal 1.2v bandgap voltage reference that is used to drive the adc. the analog front end multiplexer selects the input to the adc. the selection to the input of th e adc is either a single-ended v bus measurement or a fully diff erential measurement across a shunt resistor. the digital block contains controllable registers, i 2 c serial communication circuitry and a st ate machine. the state machine controls the behavior of the adc ac quisition, whether the acquisition is triggered or continuous. a more detailed description of the state machine states can be found in ? mode: operating mode ? on page 15 . pin descriptions a1 a1 is the address select pin. a1 is one of two i 2 c/smbus slave address select pins that are mu ltilogic programmable for a total of 16 different address combinations. there are four selectable levels for a1, vcc, gnd, scl/smbclk, and sda/smbdat. see table 22 for more details in setting the slave address of the device. a0 a0 is the address select pin. a0 is one of two i 2 c/smbus slave address select pins that are mu ltilogic programmable for a total of 16 different address combinations. there are four selectable levels for a0, vcc, gnd, scl/smbclk, and sda/smbdat. see table 22 for more details in setting the slave address of the device. ext_clk/int ext_clk/int is the external/interrupt clock pin. ext_clk/int is a bidirectional pin. the pin provides a connection to the system clock. the system clock is connected to the adc. the acquisitions rate of the adc can be varied through the ext_clk/int pin. the pin functionality is set through a control register bit. when the ext_clk/int pin is configured as an output, the pin functionality becomes an interrup t flag to connecting devices. ext_clk/int pin as an output re quires a pull-up resistor to a power supply, up to 20v, for proper operation. the internal threshold detectors (ov sh /uv sh /ov b /uv b ) signal level relative to the measured value determines the state of the int pin. sda/smbdat sda/smbdat is the serial data input/output pin. sda/smbdat is a bidirectional pin used to tran sfer data to and from the device. the pin is an open-drain output and may be wired with other open-drain/collector outputs. th e open-drain output requires a pull-up resistor for proper functionality. the pull-up resistor should be connected to vcc of the device. scl/smbclk scl/smbclk is the serial cloc k input pin. the scl/smbclk input is responsible for clocking in all data to and from the device. vcc vcc is the positive supply voltage pin. vcc is an analog power pin. vcc supplies power to the device. gnd gnd is the ground pin. all volt ages internal to the chip are referenced to ground. gnd should be tied to 0v for single supply applications. for dual supply applications, the pin should be connected to the most negative voltage in the application. vbus vbus is the power bus voltage input pin. the pin should be connected to the desired power supply bus to be monitored. vinp vinp is the shunt voltage monitor positive input pin. the pin connects to the most positive voltage of the current shunt resistor. vinm vinm is the shunt voltage monitor negative input pin. the pin connects to the most negative voltage of the current shunt resistor.
isl28022 14 fn8386.7 october 2, 2015 submit document feedback register descriptions table 2 is the register map for the device. the table describes the function of each register and it s respective value. the addresses are sequential and the register si ze is 16 bits (2 bytes) per address. configuration register the configuration register ( table 3 ) controls the functionality of the chip. adc measurable range, converter acquisition times, converter resolution and state machine modes are configurable bits within this register. rst: reset bit configuring the reset bit (bit15) to a 1 generates a system reset that initializes all registers to their default values and performs a system calibration. brng: bus voltage range bits 13 and 14 of the configur ation register sets the bus measurable voltage range. table 4 shows the brng bit configurations versus the allowable full-scale measurement range. the shaded row is the power-up default. pg: pga (shunt voltage only) bits 11 and 12 of the configuration register determines the shunt voltage measurement range. table 5 shows the pga bit configurations versus the allowable full-scale measurement range. the shaded row is the power-up default. table 2. isl28022 register descriptions register address (hex) register name function power-on reset value (hex) access 00 configuration power-on reset, bus and shunt ranges, adc acquisition times, mode configuration 799f r/w 01 shunt voltage shunt voltage measurement value 0000 r 02 bus voltage bus voltage measurement value 0000 r 03 power power measurement value 0000 r 04 current current measurement value 0000 r 05 calibration register register used to enable current and power measurements. 0000 r/w 06 shunt voltage threshold min/max shunt thresholds 7f81 r/w 07 bus voltage threshold min/max v bus thresholds ff00 r/w 08 dcs interrupt status threshold interrupts 0000 r/w 09 aux control register register to control the interrupts and external clock functionality 0000 r/w table 3. configuration register bit d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name rst brng1 brng0 pg1 pg0 badc3 badc2 badc1 ba dc0 sadc3 sadc2 sadc1 sadc0 mode2 mode1 mode0 table 4. brng bit settings brng1 brng0 usable full scale range (v) 00 16 01 32 10 60 1 1 60 table 5. pga bit settings pg1 pg0 gain range (mv) 00140 0 1 2 80 1 0 4 160 1 1 8 320
isl28022 15 fn8386.7 october 2, 2015 submit document feedback badc: bus adc resolution/averaging bits [10:7] of the configuration register sets the adc resolution/ averaging when the adc is configured in the v bus mode. the adc can be configured versus bit accuracy. the bit accuracy selections range from 12 to 15 bits. the adc is configurable versus the number of averages. the selection ranges from 2 to 128 samples. table 6 shows the breakdown of each badc setting. the shaded row is the default setting upon power-up. sadc: shunt adc resolution/averaging bits [10:7] of the configuration register sets the adc resolution/ averaging when the adc is configured in the v shunt mode. the adc can be configured versus bit accuracy. the bit accuracy selections range from 12 to 15 bits. the adc is configurable versus number of averages. the selection ranges from 2 to 128 samples. table 6 shows the break down of each sadc setting. the shaded row is the defa ult setting upon power-up. mode: operating mode bits [2:0] of the configuration register controls the state machine within the chip. the state machine globally controls the overall functionality of the chip. table 7 shows the various states the chip can be configured to, as well as the mode bit definitions to achieve a desired state. the shaded row is the default setting upon power-up. table 6. adc settings, applies to both sadc and badc control adc3 adc2 adc1 adc0 mode/samples conversion time 0 x 0 0 12-bit 72s 0 x 0 1 13-bit 132s 0 x 1 0 14-bit 258s 0 x 1 1 15-bit 508s 1 0 0 0 15-bit 508s 100121.01ms 101042.01ms 101184.01ms 1100168.01ms 11013216.01ms 11106432.01ms 1 1 1 1 128 64.01ms table 7. operating mode settings mode2 mode1 mode0 mode 000power-down 0 0 1 shunt voltage, triggered 0 1 0 bus voltage, triggered 0 1 1 shunt and bus, triggered 1 0 0 adc off (disabled) 1 0 1 shunt voltage, continuous 1 1 0 bus voltage, continuous 1 1 1 shunt and bus, continuous
isl28022 16 fn8386.7 october 2, 2015 submit document feedback shunt voltage register 01h (read-only) the shunt voltage register reports the measured value across the shunt pins (vinp and vinm) into the register. the shunt register lsb is independent of pga rang e settings. the pga setting for the shunt register masks the unused most significant bit with a sign bit. for lower range of pga settings, multiple sign bits are returned by the dpm. only one sign bit should be used to calculate the measured value. tables 8 through 11 show the weights of each bit for various pga ranges. the tables should be used to calculate the measured value across the shunt pins from the binary to decimal domains. to calculate the measured decimal value across the shunt, first read the shunt voltage register. a ssume the pga setting is set to the 80mv range. for this example, the reading output by the chip is 1111 1010 0000 0101. the 80mv range has three sign bits. only one sign bit needs to be used to calculate the measured decimal value. bits 14 and 15 are omitted from the calculation. this leaves a binary reading of 11 1010 0000 0101. next, multiply each bit by its respective weight. bit0 value would be multiplied by bit0 weight (1), bit1 value*bit1 weight (2), etc. add all the multiplied values to equate to a single number. for the binary reading 11 1010 0000 0101 this equates to -1531. the lsb for a shunt register is 10v. multiplying the decimal value by the lsb weight yields the measured voltage across the shunt. a 1111 1010 0000 0101 reading equals -15.31mv measured across the shunt pins. table 8. shunt voltage register, pg gain = /8 (r ange = 11), full-scale = 320mv, 15 bits wide bit d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name sign bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 weight -32768 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 1 table 9. shunt voltage register, pg gain = /4 (r ange = 10), full-scale = 160mv, 14 bits wide bit d15 d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name sign sign bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bi t4 bit3 bit2 bit1 bit0 weight -16384 8192 4096 2048 1024 512 256 128 64 32 16 8421 table 10. shunt voltage register, pg gain = /2 (range = 01), full-scale = 80mv, 13 bits wide bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name sign sign sign bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 weight -8192 4096 2048 1024 512 256 128 64 32 16 8421 table 11. shunt voltage register, pg gain = /1 (r ange = 00), full-scale = 40mv, 12 bits wide bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name sign sign sign sign bit11 bit10 bit9 bi t8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 weight -4096 2048 1024 512 256 128 64 32 16 8 4 2 1 table 12. bus voltage register, brng = 10 or 11, full-scale = 60v, 14 bits wide bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cnvr ovf weight 8192 4096 2048 1024 512 256 128 64 32 16 8421 table 13. bus voltage register, brng = 01, full-scale = 32v, 13 bits wide bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cnvr ovf weight 4096 2048 1024 512 256 128 64 32 16 8 4 2 1 table 14. bus voltage register, brng = 00, full-scale = 16v, 12 bits wide bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cnvr ovf weight 2048 1024 512 256 128 64 32 16 8 4 2 1 table 15. calibration register, 05h bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name fs15 fs14 fs13 fs12 fs11 fs10 fs9 fs8 fs7 fs6 fs5 fs4 fs3 fs2 fs1 0
isl28022 17 fn8386.7 october 2, 2015 submit document feedback bus voltage register 02h (read-only) the bus voltage register is where the dpm reports the measured value of the v bus . there are three scale ranges possible depending on the brng setting co ntrolled from the configuration register(00h). tables 12 through 14 on page 16 are the weight bits for each brng setting. the binary value recorded in the bus voltage register is translated to a decimal value in the same way as the shunt voltage register is converted to a decimal value. equation 1 is the mathematical equation for converting the binary v bus value to a decimal value. n is the bit number. the lsb value for the v bus measurement equals 4mv across all bus range (brng) settings. cnvr: conversion ready (bit 1) the conversion ready bit indicates when the adc has finished a conversion and transferred the reading(s) to the appropriate register(s). the cnvr is only operable when the dpm is set to one of three trigger modes. the cnvr is at a high state when the conversion is in progress. the cnvr transitions and remains at a low state when the conversion is complete. the cnvr bit is initialized or re initialized in the following ways: 1. writing to the configuration register. 2. reading from power register. ovf: math overflow flag (bit0) the math overflow flag (ovf) is a bit that is set to indicate the current or power data being read from the dpm is over-ranged and meaningless. calibration register 05h (read/write) to accurately read the current and power measurements from the chip, the calibration register needs to be programmed. the calibration register value is calculated as follows: 1. calculate the full-scale current ra nge that is desired. this is calculated using equation 2 . r shunt is the value of the shunt resistor. v shunt is the full-scale setting that is desired. in most cases, it is the pga full-scale range (320mv, 160mv, 80mv and 40mv) that the dpm is programmed to. 2. from the current full-scale range, the current lsb is calculated using equation 3 . current full-scale is the outcome from equation 2 . adc res is the resolution of shunt voltage reading. the value is determined by the sadc setting in configuration register. sadc setting equal to 3 and greater will have a 15-bit resolution. the adc res value equals 2 15 or 32768. 3. from equation 3 , the calibration resister value is calculated using equation 4 . the resolution of the math that is processed internally in the dpm is 4096 or 12 bits of resolution. the v shunt lsb is set to 10v. equation 4 yields a 16-bit binary number that can be written to the calibration register. the calibration value can only be 15 bits due to the adc res value. bit 0 of the calibration register is fixed to a value of 0. the calibration register format is represented in table 15 . current register 04h (read-only) once the calibration register (05h) is programmed, the output current is calculated using equation 5 : bit is the returned value of each bit from the current register either 1 or a 0. the weight of each bit is represented in table 16 . n is the bit number. the current lsb is the value calculated from equation 3 . power register 03h (read-only) the power register only has meaning if the calibration register (05h) is programmed. the units for the power register are in watts. the power is calculated using equation 6 : bit is the returned value of each bit from the power register either 1 or a 0. the weight of each bit is represented in table 17 . n is the bit number. the power lsb is calculated from equation 7 : if v bus range, brng, is set to 60v, the power equation in equation 6 is multiplied by 2. threshold registers the shunt voltage or v bus threshold registers are used to set the min/max threshold limits that will be tested versus v shunt or v bus readings. measurement readin gs exceeding the respective v shunt or v bus limits, either above or below, will set a register flag and perhaps an external interrupt depending on the configuration of the interrupt enable bit (intren) in register 09h. the testing of the adc reading versus the respective threshold limits occurs once per adc conversion. (eq. 1) v bus 2 15 n bit n bit_weight n ? ?? ? ? ? ? ? ? ? ? ? ? vbus lsb ? (eq. 2) current fs vshunt fs r shunt (eq. 3) current lsb current fs adc res (eq. 4) calreg val integer math res vshunt lsb ? current lsb r shunt ? ?? ? ? ? ? ? ? calreg val integer 0.04096 current lsb r shunt ? ?? ? ? ? ? ? ? current 0 15 n bit n bit_weight n ? ?? ? ? ? ? ? ? ? ? ? ? current lsb ? (eq. 5) (eq. 6) power 0 15 n bit n bit_weight n ? ?? ? ? ? ? ? ? ? ? ? ? power lsb ? 5000 ? ?? ?? ? (eq. 7)
isl28022 18 fn8386.7 october 2, 2015 submit document feedback shunt voltage threshold register 06h (read/write) the v shunt minimum and maximum threshold limits are set using one register. the shunt value readings are either positive or negative. d15 and d7 bits of table 18 are given to represent the sign of the limit. smx bits repr esent the upper limit threshold. smn represents the lower threshold limit. equation 8 is the calculation used to convert the v shunt threshold binary value to decimal. bit is the value of each bit set in the shunt threshold register. the value is either 1 or a 0. the weight of each bit is represented in table 18 . n is the bit number. the shunt voltage threshold lsb is 2.56mv. vs thresh 0 7 n bit n bit_weight n ? ?? ? ? ? ? ? ? ? ? ? ? vsthresh lsb ? (eq. 8) table 16. current register, 04h bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 namebit 15bit14bit13bit12bit11bit10bit9bit8bit7bit6bit5bit4bit3bit2bit1bit0 weight -32768 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 1 table 17. power register, 03h bit d15 d14 d13 d12 d11 d10 d9d8d7d6d5d4d3d2d1d0 name pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 weight 32768 16384 8192 4096 2048 1024 512 256 128 64 32 16 8421 table 18. shunt voltage threshold register, 06h bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name sign smx6 smx5 smx4 smx3 smx2 smx1 sm x0 sign smn6 smn5 smn4 smn3 smn2 smn1 smn0 weight -128 64 32 16 8 4 2 1 -128 64 32 16 8 4 2 1 table 19. bus voltage threshold register, 07h bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name bmx7 bmx6 bmx5 bmx4 bmx3 bmx2 bmx1 bmx0 bmn7 bmn6 bmn5 bmn4 bmn3 bmn2 bmn1 bmn0 weight 128 64 32 16 8 4 2 1 128 64 32 16 8 4 2 1 table 20. interrupt status register, 08h bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name na na na na na na na na na na na na smxw smnw bmxw bmnw weight0000000000000000 table 21. aux control register, 09h bitd15d14d13d12d11d10d9 d8 d7 d6 d5d4d3d2d1d0 name na na na na na na na forceintr intren extclken extclkdiv[5:0] weight0000000 0 0 0 000000
isl28022 19 fn8386.7 october 2, 2015 submit document feedback bus voltage threshold register 07h (read/write) the v bus minimum and maximum threshold limits are set using one register. the v bus value readings range from 0v to 60v. table 19 on page 18 shows the register configuration and bit weights for the v bus threshold register. bmx bits represent the upper limit threshold. bmn repres ents the lower threshold limit. equation 9 is the calculation used to convert the v bus threshold binary value to decimal. bit is the value of each bit set in the v bus threshold register. the value is either 1 or a 0. the weight of each bit is represented in table 19 . n is the bit number. the v bus voltage threshold lsb is 256mv. interrupt status register 08h (read/write) the interrupt status register consists of a series of bit flags that indicate if an adc reading has ex ceeded the readings respective limit. a 1 or high reading from a warning bit indicates the reading has exceeded the limit. to clear a warning, write a 1 or high to the set warning bit. table 20 on page 18 shows the definition of the interrupt status register. bmnw is the bus voltage minimum warning. a 1 reading for this bit indicates the bus reading is below the bus voltage minimum threshold limit. bmxw is the bus voltage maximum warning. a 1 reading for this bit indicates the bus reading is above the bus voltage maximum threshold limit. smnw is the shunt voltage minimum warning. a 1 reading for this bit indicates the shunt reading is below the shunt voltage minimum threshold limit. smxw is the shunt voltage maximum warning. a 1 reading for this bit indicates the shunt reading is above the shunt voltage maximum threshold limit. aux control register 09h (read/write) the aux control register controls the functionality of the extclk/int pin of the isl28022. table 21 shows the definition of the register. forceintr is the force interrupt bit. programming a 1 to the bit will force a 0 or a low at the extclk/int pin. intren is the interrupt enable bit. programming a 1 to the bit will allow for a threshold measurement violation to set the state of the extclk/int pin. with the intren set, any flag set from the interrupt status register will ch ange the state of the extclk/int pin from 1 to a 0. exclken is the external clock enab le bit. setting the bit enables the external clock. this also ch anges the extclk/int pin from an output to an input. the internal os cillator will shut down when the bit is enabled. extclkdiv are the external clock di vider bits. the bits control an internal clock divider that are us eful for fast system clocks. the internal clock frequency from pin to chip is represented in equation 10 : f extclk is the frequency of the signal driven to the extclk/int pin. extclkdiv is the decimal value of the clock divide bits. serial interface the isl28022 supports a bidirectional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is the master and the device being controlled is the slave. the master always initiates data transfers and provides the clock for both transmit and receive operations. therefore, the isl28022 operates as a slave device in all applications. the isl28022 uses two bytes to transfer all reads and writes. all communication over the i 2 c interface is conducted by sending the msbyte of each byte of data first, followed by the lsbyte. protocol conventions for normal operation, data states on the sda line can change only during scl low periods. sda state changes during scl high are reserved for indicating start and stop conditions (see figure 27 ). on power-up of the isl28022, the sda pin is in the input mode. all i 2 c interface operations must begin with a start condition, which is a high-to-low transition of sda while scl is high. the isl28022 continuously monitors the sda and scl lines for the start condition and does not resp ond to any command until this condition is met (see figure 27 ). a start condition is ignored during the power-up sequence. all i 2 c interface operations must be terminated by a stop condition, which is a low-to-high transition of sda while scl is high (see figure 27 ). a stop condition at the end of a read operation or at the end of a write operation places the device in its standby mode. smbus support the isl28022 supports smbus protocol, which is a subset of the global i 2 c protocol. smbclk and smbdat have the same pin functionality as the scl and sda pins, respectively. the smbus operates at 100khz. (eq. 9) vb thresh 0 7 n bit n bit_weight n ? ?? ? ? ? ? ? ? ? ? ? ? vbthresh lsb ? freq internal f extclk extclkdiv 1 ? ()2 ? (eq. 10)
isl28022 20 fn8386.7 october 2, 2015 submit document feedback figure 27. valid data change s, start and stop conditions figure 28. acknowledge response from receiver figure 29. byte write sequence (s lave address indicated by nnnn) sda scl start data data stop stable change data stable sda output from transmitter sda output from receiver 8 1 9 start ack scl from master high high impedance s t a r t identification byte data byte a c k signals from the master signals from the isl28022 a c k 10 0 0n write signal at sda 0000 nnn address byte s t o p data byte a c k a c k
isl28022 21 fn8386.7 october 2, 2015 submit document feedback device addressing following a start condition, the ma ster must output a slave address byte. the 7 msbs are the device identifiers. the a0 and a1 pins control the bus address (these bits are shown in table 22 ). there are 16 possible combinations depe nding on the a0/a1 connections. the last bit of the slave address byte defines a read or write operation to be performed. when this r/w bit is a ?1?, a read operation is selected. a ?0? sele cts a write operation (refer to figure 29 ). after loading the entire slave address byte from the sda bus, the isl28022 compares the loaded value to the internal slave address. upon a correct compare, the device outputs an acknowledge on the sda line. following the slave byte is a one byte word address. the word address is either supplied by the master device or obtained from an internal counter. on power-up, the internal address counter is set to address 00h, so a current address read starts at address 00h. when required, as part of a random read, the master must supply the one word address byte, as shown in figure 30 . in a random read operation, the slave byte in the ?dummy write? portion must match the slave byte in the ?read? section. for a random read of the registers, th e slave byte must be ?100nnnnx? in both places. table 22. i 2 c slave addresses a1 a0 slave address gnd gnd 1000 000 gnd vcc 1000 001 gnd sda 1000 010 gnd scl 1000 011 vcc gnd 1000 100 vcc vcc 1000 101 vcc sda 1000 110 vcc scl 1000 111 sda gnd 1001 000 sda vcc 1001 001 sda sda 1001 010 sda scl 1001 011 scl gnd 1001 100 scl vcc 1001 101 scl sda 1001 110 scl scl 1001 111 broadcast address 0111 111 figure 30. read sequence (slave address shown as nnnn) signals from the master signals from the slave signal at sda s t a r t identification byte with r/w = 0 address byte a c k a c k 0 s t o p 1 identification byte with r/w = 1 a c k s t a r t second read data byte first read data byte a c k 10 0 nnnn 10 0 nn nn
isl28022 22 fn8386.7 october 2, 2015 submit document feedback write operation a write operation requires a start condition, followed by a valid identification byte, a valid address byte, two data bytes and a stop condition. the first data byte contains the lsb of the data, the second contains the msb. after each of the four bytes, the isl28022 responds with an ack. at this time, the i 2 c interface enters a standby state. read operation a read operation consists of a thr ee byte instruction, followed by two data bytes (see figure 30 on page 21 ). the master initiates the operation issuing the following sequence: a start, the identification byte with the r/w bit set to ?0?, an address byte, a second start and a second identification byte with the r/w bit set to ?1?. after each of the three bytes, the isl28022 responds with an ack. then the isl28022 transmits two data bytes as long as the master responds with an ack during the scl cycle following the eighth bit of the first byte. the master terminates the read operation (issuing no ack then a stop condition) following the last bit of the second data byte (see figure 30 on page 21 ). the data bytes are from the memory location indicated by an internal pointer. this pointer?s in itial value is determined by the address byte in the read operatio n instruction and increments by one during transmission of each pair of data bytes. the highest valid memory location is 09h, re ads of addresses higher than that will not return useful data. broadcast addressing the dpm has a feature that allows the user to configure the settings of all dpm chips at once. for example, a system has 16 dpm chips connected to an i 2 c bus. a user can set the range or initiate a data acquisition in one i 2 c data transaction by using a slave address of 0111 111. the broadcast feature saves time in configuring the dpm as well as measuring signal parameters in time synchronization. the broadc ast should not be used for dpm read backs. this will cause all devices connected to the i 2 c bus to talk to the master simultaneously. i 2 c clock speed the device supports high-speed digital transactions up to 3.4mbs. to access the high speed i 2 c feature, a master byte code of 0000 1xxx is attached to the beginning of a standard frequency read/write i 2 c protocol. the x in the master byte signifies a do not care state. x can either equal a 0 or a 1. the master byte code should be cloc ked into the chip at frequencies equal or less than 400khz. the master code command configures the internal filters of the isl28022 to permit data bit frequencies greater than 400khz. once the master code has been clocked into the device, the protocol for a standard read/ write transaction is followed. the frequency at which the standard protocol is clocked in at can be as great as 3.4mhz. a stop bit at the end of a standard protocol w ill terminate the high speed transaction mode. appendin g another standard protocol serial transaction to the data string without a stop bit, will resume the high speed di gital transaction mode. figure 32 illustrates the data sequence for the high speed mode. figure 31. slave address, word address, and data bytes d15 d14 d13 d10 d12 d11 d9 d8 a0 a7 a2 a4 a3 a1 data byte 1 a6 a5 1 00 n n n r/w n word address d7 d6 d5 d2 d4 d3 d1 d0 slave address byte data byte 2 signals from the master signals from the isl28025 signal at sda s t a r t master code slave address identification byte a c k x s t o p address byte a c k write/read 00 0 01xx 00 0 0 s t a r t data byte data byte a c k a c k fclk 400khz fclk up to 3.4mhz terminates hs mode n 10 0 nnnn
isl28022 23 fn8386.7 october 2, 2015 submit document feedback signal integrity the purity of the signal being measured by the isl28022 is not always ideal. environmental noise or noise generated from a regulator can degrade the measurement accuracy. the isl28022 maintains a high cmrr ratio from dc to approximately 10khz, as shown in figure 33 . the cmrr vs frequency graph best represents the response of the isl28022 when an aberrant sign al is applied to the circuit. the graph was generated by shor ting the isl28022 input without any filtering and applying a 0v to 10v triangle wave to the shunt inputs, vinp and vinm. the voltage shunt measurement was recorded for each frequency applied to the shunt input. the cmrr can be improved by desi gning a filter stage before the isl28022. the purpose of the filter stage is to attenuate the amplitude of the unwanted signal to the noise level of the isl28022. figure 34 is a simple filter example to attenuate unwanted signals. csh and rsh are single pole rc filters that differentially attenuate unwanted signals to the isl28022. most power monitoring applications require a shunt resistor to be low in value to measure large currents. for small shunt resistors, a large value capacitor is required to attenuate low frequency signals. most large value capacitors ar e not offered in space saving packages. the corner frequency of the differential filter, csh and rsh, should be designed for higher value frequency filtering. r 1 and c 1 for both inputs are single ended low pass filters. the value of the series resistor to the isl28022 can be a larger value than the shunt resistor, r sh . a larger series resistor to the input allows for a lower cutoff frequency filter design to the isl28022. the isl28022 can source up to 20a of transient current in the measurement mode. the transient or switching offset current can be as large as 10a. the switching offset current combined with the series resistance, r 1 , creates an error offset voltage. a balance of the value of r 1 and the shunt measurement error should be achieved for this filter design. the common mode voltage of the shunt input stage ranges from 0v to 60v. the capacitor voltage rating for c 1 and csh should comply with the nominal voltage being applied to the input. measurement stability vs acquisition time the badc and sadc bits within the configuration register configures the conversion time and accuracy for the bus and shunt inputs respectively. the faster the conversion time the less accuracy and more noise introd uced into the measurement. figure 35 is a graph that illustrates the shunt measurement variability versus a set sadc mode. the standard deviation of 2048 shunt v os measurements is used to quantify the measurement variability of each mode. fast transients a small isolation resistor plac ed between isl28022 inputs and the source is recommended. in hot swap or other fast transient events, the amplitude of a signal can exceed the recommended operating voltage of the part du e to the line inductance. the isolation resistor creates a low pa ss filter between the device and the source. the value of the isolation resistor should not be too large. a large value isolation resistor can effect the measurement accuracy. the offset current for shunt input can be as large as 10a. the value of the isolation resistor combined with the offset current creates an error offset voltage at the shunt input. the input of the bus channel is connected to the top of a precision resistor divider. the accuracy of the resistor divider determines the gain error of the bus channel. the input resistance of the bus channel is 600k . placing an isolation resistor of the 10 will change the gain error of the bus channel by 0.0016%. figure 33. cmrr vs frequency figure 34. simplified filter design to improve noise performance to the isl28022 80 85 90 95 100 105 110 115 120 125 130 10 100 1k 10k 100k 1m frequency (hz) cmrr (db) load rsh from source isl28022 r1 r1 csh c1 c1 figure 35. measurement stability vs sadc mode 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sadc mode v shunt v os sigma (mv)
isl28022 24 fn8386.7 october 2, 2015 submit document feedback external clock an externally controlled clock allows measurements to be synchronized to an event that is time dependent. the event could be application generated, such as timing a current measurement to a charging capacitor in a switch regulator application or the event could be environmental. a voltage or current measurement may be susceptible to crosstalk fr om a controlled source. instead of filtering the environmental noise from the measurement, another approach would be to synchronize the measurement to the source. the variability and a ccuracy of the measurement will improve. the isl28022 has the functionality to allow for synchronization to an external clock. the speed of the external clock combined with the choice of the internal chip frequency division value determines the acquisition times of the adc. the internal system clock frequency is 500khz. the inte rnal system clock is also the adc sampling clock. the acquisit ion times scale linearly from 500khz. for example, an external clock frequency of 1mhz with a frequency divide setting of 2 results in acquisition times that equals the internal oscillator frequency when enabled. the internal clock frequency of th e isl28022 should not exceed 500khz. the adc modulator is optimized for frequencies of 500khz and below. operating in ternal clock frequencies above 500khz result in measurement accuracy errors due to the modulator not having enough time to settle. suppose an external clock frequenc y of 1.0mhz is applied with a divide by 8 internal frequency se tting, the system clock speed is 125khz or 4x slower than internal system clock. the acquisition times for this example will increase by 4. for a s(b)adc setting of 3, the isl28022 will have an acquisition time of 2.032ms instead of 508s. the eclk/int pin connects to a buffer that drives a d-flip flop. figure 37 illustrates a simple schematic of the eclk/int pin internal connection. the series of divide by 2 configured d-flip flops are controlled by the clkdiv bits from the aux control register. the buffer is a schmitt triggered buffer. the bandwidth of the buffer is 4mhz. figure 38 shows the bandwidth of the eclk/int pin. the v shunt measurement error degrades at eclk frequencies above 4mhz. it is recommended that the eclk does not exceed 4mhz. at eclk frequencies below 2.5mhz or internal clock frequencies of 208khz, the clock frequency to modulator is too slow allowing the charged capacitors to discharge due to parasitic leakages. the capacitor discharge results in a measurement error. over-ranging it is not recommende d to operate the isl28022 outside the set voltage range. in the event of measuring a shunt voltage beyond the maximum set range (320mv) and lower than the clamp voltage of the protection diode (1v), the measured output reading may be within the accepted range but will be incorrect. figure 36. simplified sc hematic of the isl28022 synchronized to a pwm source i 2 c smbus a1 scl sda vinp vinm gnd rsh adc 16-bit sw mux eclk reg map vcc vbus a0 isl28022 dpm load to mcu function generator 3.3v + - vth eclk/int +1 fclk_sys 2x -1 0 1 2 3 4 5 1 10 external clock frequency (mhz) v shunt measurement error normalized (%) clkdiv = 5 ( 12) sadc = 3
isl28022 25 fn8386.7 october 2, 2015 submit document feedback shunt resistor selection in choosing a sense resistor, th e following resistor parameters need to be considered: the resistor value, resistor temperature coefficient and resistor power rating. the sense resistor value is a function of the full-scale voltage drop across the shunt resistor and the maximum current measured for the application. the isl28022 has 4 voltage ranges that are controlled by programming the pga bits within the configuration register. the pga bits control the voltage range for the v shunt input (vinp-vinm) of the isl28022. once the voltage range for the input is chosen and the maximum measurable current is known, the sense resistor value is calculated using equation 11 : in choosing a sense resistor, th e sense resistor power rating should be taken into consideration. the physical size of a sense resistor is proportional to the power rating of the resistor. the maximum power rating for the measurement system is calculated as the v shunt _ range multiplied by the maximum measurable current expected. the power rating equation is represented by equation 12 : a general rule of thumb is to multiply the power rating calculated in equation 12 by 2. this allows the sense resistor to survive an event when the current passing through the shunt resistor is greater than the measurable ma ximum current. the higher the ratio between the power rating of the chosen sense resistor and the calculated power rating of the system ( equation 12 ), the less the resistor will heat up in high-current applications. the temperature coefficient (tc) of the sense resistor directly degrades the current measurement accuracy. the surrounding temperature of the sense resistor and the power dissipated by the resistor will cause the sense resistor value to change. the change in resistor temperature with respect to the amount of current that flows through the resistor, is directly proportional to the ratio of the power rating of the resistor versus the power being dissipated. a change in se nse resistor temperature results in a change in sense resistor value. overall, the change in sense resistor value contributes to th e measurement accuracy for the system. the change in a resistor value due to a temperature rise can be calculated using equation 13 : ? temperature is the change in temperature in celsius. rsense tc is the temperature coefficient rating for a sense resistor. r sense is the resistance value of the sense resistor at the initial temperature. table 23 is a shunt resistor referenc e table for select full-scale current measurement ranges (imeas max ). the table also provides the minimum rating for each shunt resistor. it is often hard to readily purchase shunt resistor values for a desired measurable current range. either the value of the shunt resistor does not exist or the power rating of the shunt resistor is too low. a means of circumventing the problem is to use two or more shunt resistors in parallel to set the desired current measurement range. for example, an application requires a full-scale current of 50a with a maximum voltage drop across the shunt resistor of 40mv. table 23 shows this requires a sense resistor of 0.8m , 2w resistor. assume the power ratings and the shunt resistor values to choose from are 1m ? 1w, 2m /1w, and 4m /1w. let?s use a 1m and a 4m resistor in parallel to create the shunt resistor value of 0.8m . figure 39 shows an illustration of the shunt resistors in parallel. (eq. 11) r sense v shunt_range imeas max p res_rating v shunt_range imeas max ? ? r sense r sense rsense tc ?? temperature ? /4w 800 /8w 1.6k /16w 3.2k / 32w 1ma 40 /40w 80 /80w 160 /160w 320 / 320w 10ma 4 /400w 8 /800w 16 /1.6mw 32 / 3.2mw 100ma 400m /4mw 800m /8mw 1.6 /16mw 3.2 / 30mw 500ma 80m /20mw 160m /40mw 320m / 80mw 640m / 160mw 1a 40m /40mw 80m /80mw 160m / 160mw 320m / 320mw 5a 8m /200mw 16m /400mw 32m / 800mw 64m / 1.6w 10a 4m /400mw 8m /800mw 16m /1.6w 32m / 3.2w 50a 0.8m /2w 1.6m /4w 3.2m /8w 6.4m / 16w 100a 0.4m /4w 0.8m /8w 1.6m /16w 3.2m / 32w 500a 0.08m /20w 0.16m /40w 0.32m /80w 0.64m / 160w 0.001 0.004 figure 39. a simplified schema tic illustrating the use of two shunt resistors to create a desired shunt value
isl28022 26 fn8386.7 october 2, 2015 submit document feedback the power to each shunt resistor should be calculated before calling a solution complete. the power to each shunt resistor is calculated using equation 14 : the power dissipated by the 1m resistor is 1.6w. 400mw is dissipated by the 4m resistor. 1.6w exceed s the rating limit of 1w for the 1m sense resistor. another approach would be to use three shunt resistors in parallel as illustrated in figure 40 . using equation 14 , the power dissipated to each shunt resistor yields 0.8w for the 2m shunt resistors and 0.4w for the 4m shunt resistor. all shunt resistors are within the specified power ratings. lossless current sensing (dcr) a dcr sense circuit is an alternative to a sense resistor. the dcr circuit utilizes the parasitic resistance of an inductor to measure the current to the load. a dcr circuit remotely measures the current through an inductor. the lack of components in series with the regulator to the load makes the circuit lossless. a properly matched dcr circuit has an equivalent circuit seen by the adc equals to r dcr in figure 41 . before deriving the transfer function between the inductor cu rrent and voltage seen by the isl28022, let?s review the definition of an inductor and capacitor in the laplacian domain. x c is the impedance of a capacitor related to the frequency and x l is the impedance of an inductor related to frequency. equals to 2* *f. f is the chop frequency dict ated by the regulator. using ohms law, the voltage across the dcr circuit in terms of the current flowing through the inductor is defined in equation 16 . in equation 16 , r dcr is the parasitic resistance of the inductor. the voltage drop across the indu ctor (lo) and the resistor (r dcr ) circuit is the same as the voltage drop across the resistor (r sen ) and the capacitor (c sen ) circuit. equation 17 defines the voltage across the capacitor (v csen ) in terms of the inductor current (i l ). the relationship between the inductor load current (i l ) and the voltage across capacitor simplifi es if the following component selection holds true: if equation 18 hold true, the numerator and denominator of the fraction in equation 17 cancels reducing the voltage across the capacitor to the equation represented in equation 19 . most inductor datasheets will sp ecify the average value of the r dcr for the inductor. r dcr values are usually sub 1m with a tolerance averaging 8%. common chip capacitor tolerances average to 10%. inductors are constructed out of metal. metal has a high temperature coefficient. the temperature drift of the inductor value could cause the dcr circuit to be untuned. an untuned circuit results in inaccurate cu rrent measurements along with a chop signal bleeding into the measurement. to counter the temperature variance, a te mperature sensor may be incorporated into the design to track the change in component values. a dcr circuit is good for gross current measurements. as discussed, inductors and capacitors have high tolerances and are temperature dependent which will result in less than accurate current measurements. in figure 41 , there is a resistor in series with the isl28022 negative shunt terminal, vinm, with the value of r sen + r dcr. the resistor?s purpose is to counter the effects of the bias current from creating a voltage offset at the input of the adc. layout the layout of a current measuring system is equally important as choosing the correct sense resistor and the correct analog converter. poor layout techniques can result in severed traces, signal path oscillations, magnetic contamination, which all contribute to poor system performance. figure 41. a simplified circuit example of a dcr (eq. 14) p shuntres v shunt_range 2 r sense 0.002 0.004 0.002 vinp vinm lo r dcr c se n r se n dcr circuit adc 16-bit fb phase r se n + r dcr buck regula tor load (eq. 15) x c f () 1 j ? f () ? c ? x l f () j ? f () ? l ? (eq. 16) v dcr f () r dcr j ? f () ? l ? ? ? ? i l ? (eq. 17) v c f () j ? f () ? l ? r dcr ? ?? 1j ? f () ? c sen ? r sen ? ? ? ? ? ? ? ? i l ? r dcr 1 jwf () ? l ? () r dcr ? ? ? ? ? ? ? 1j ? f () ? c sen ? r sen ? ? ? ? ? ? ? ? ? ? ? i l ? (eq. 18) l r dcr c sen r sen ? (eq. 19) v c r dcr i l ?
isl28022 27 fn8386.7 october 2, 2015 submit document feedback trace width matching the current carrying dens ity of a copper trace with the maximum current that will pass through is critical in the performance of the system. neglecting the current carrying capability of a trace will result in a large temperature rise in the trace, and the loss in system efficiency due to the increase in resistance of the copper trace. in extreme cases, the copper trace could be severed because the trace could not pass the current. the current carrying capability of a trace is calculated using equation 20 : i max is the largest current expected to pass through the trace. ? t is the allowable temperature rise in celsius when the maximum current passes through the trace. trace thickness is the thickness of the trace specified to the pcb fabricator in mils. a typical thickness for general current carrying applications (<100ma) is 0.5oz copper or 0.7mils. for larger currents, the trace thickness should be greater than 1.0oz or 1.4mils. a balance between thickness, width and cost needs to be achieved for each design. the coefficient k in equation 20 changes depending on the trace location. for external traces, the value of k equals 0.048 while for internal traces the value of k reduces to 0.024. the k values and equation 20 are stated per the ansi ipc-2221(a) standards. trace routing it is always advised to make the distance between voltage source, sense resistor and load as close as possible. the longer the trace length between components will result in voltage drops between components. the additional resistance will reduce the efficiency of a system. the bulk resistance, ? , of copper is 0.67 /in or 1.7 /cm at +25c. the resistance of trac e can be calculated from equation 21 : figure 42 illustrates each dimension of a trace. for example, assume a trace has 2oz of copper or 2.8mil thickness, a width of 100mil an d a length of 0.5in. using equation 21 , the resistance of the trace is approximately 2m . assume 1a of current is passi ng through the trace. a 2mv voltage drop would result from trace routing. current flowing through a conducto r will take the path of least resistance. when routing a trace, avoid orthogonal connections for current bearing traces. orthogonal routing for high current flow traces will result in current crowding, localized heatin g of the trace and a change in trace resistance (see figure 43 ). the utilization of arcs and 45 trac es in routing large current flow traces will maintain uniform current flow throughout the trace. figure 44 illustrates the routing technique. (eq. 20) trace width imax k ? t 0.44 ? ? ? ? ? ? ? 1 0.725 trace thickness r trace ? trace length trace width trace thickness ? ? t r a c e l e n g t h trace width trace thickness figure 42. illustration of the trace dimensions for a strip line trace current flow figure 43. avoid routing or thogonal connections for traces that have high current flows c u r r e n t f l o w current flow figure 44. avoid routing orthogonal connections for traces that have high current flows
isl28022 28 fn8386.7 october 2, 2015 submit document feedback connecting sense traces to the current sense resistor ideally, a 4 terminal current sense resistor would be used as the sensing element. four terminal se nsor resistors can be hard to find in specific values and in sizes. often a two terminal sense resistor is designed into the application. sense lines are high impedance by definition. the connection point of a high impedance line reflects the voltage at the intersection of a current bearing trace and a high impedance trace. the high impedance trace should connect at the intersection where the sense resistor meets the landing pad on the pcb. the best place to make curr ent sense line connection is on the inner side of the sense resistor footprint. the illu stration of the connection is shown in figure 45 . most of the current flow is at the outer edge of the footprint. the current ceases at the point the sense resistor connects to the landing pad. assume the sense resistor connects at the middle of th e each landing pa d, this leaves the inner half of the ea ch landing pad with little current flow. with little current flow, the inner half of each landing pad is classified as high impedance and perfect for a sense connection. current sense resistors are often smaller than the width of the traces that connect to the footpr int. the trace connecting to the footprint is tapered at a 45 angle to control the uniformity of the current flow. magnetic interference the magnetic field generated from a trace is directly proportional to the current passing through the trace and the distance from the trace the field is being measured at. figure 46 illustrates the direction the magnetic field flows versus current flow. the equation in figure 46 determines the magnetic field, b, the trace generates in relation to the current passing through the trace, i, and the distance the magnetic field is being measured from the conductor, r. the permeability of air, o , is 4 ? *10 -7 h/m. when routing high-current traces, avoid routing high impedance traces in parallel with high-current bearing traces. a means of limiting the magnetic interference from high-current traces is to closely route the paths connected to and from the sense resistor. the magnetic fields will cancel outside the two traces and add between the two traces. figure 47 illustrates a layout that is less sensitive to magnetic field interference. if possible, do not cross traces with high-current. if a trace crossing cannot be avoided, cr oss the trace in an orthogonal manor and the furthest layer from the current bearing trace. the interference from the current bearing trace will be limited. sense resistor sense trace sense trace landing pad landing pad current bearing trace current bearing trace figure 45. connecting the sense lines to a current sense resistor figure 47. closely routed traces that connect to the sense resistor reduces the magnetic interference sourced from the current flowing through the traces b ? o i ? 2 ? ? r ? sense resistor s e n s e t r a c e s e n s e t r a c e l a n d i n g p a d l a n d i n g p a d current flow current flow t o t h e s e n s e r e s i s t o r f r o m t h e s e n s e r e s i s t o r b to b from ? b to b from ? b to b from ? to sense circuitry
isl28022 29 fn8386.7 october 2, 2015 submit document feedback a trace as a sense resistor in previous sections, the resist ance and the current carrying capabilities of a trace were discussed. in high current sense applications, a design may utiliz e the resistivity of a current sense trace as the sense resistor. this section will discuss how to design a sense resistor from a copper trace. suppose an application needs to measure current up to 200a. the design requires the least amount of voltage drop for maximum efficiency. the full-scale voltage range of 40mv (pga 00) is chosen. from ohms law, the sense resist or is calculated to be 200 . the power rating of the resistor is ca lculated to be 8w. assume the pcb trace thickness of the board equals 2oz/2.8mils and the maximum temperature rise of the trace is 20c. using equation 20 on page 27 , the calculated trace width is 2.192in. the trace width, thickness and the desired sense resistor value is known. utilizing equation 21 on page 27 , the trace length is calculated to be 1.832in. figure 48 illustrates a layout example of a current sense resistor defined by a pcb trace. the serpentine pattern of the resistor reduces current crowding as we ll as limiting the magnetic interference caused by the current flowing through the trace. the width of the trace in figure 48 illustration would equal 2.192in and the length between th e sense lines equals 1.832in. the width of the resistor is long for some applications. a means of shortening the trace width is to connect two traces in parallel. for calculation ease, assume the resistive traces are routed on the outside layers of a pcb. using equations 20 and 21 on page 27 , the width of the trace is reduced from 2.192in to 1.096in. when using multiple layers to create a trace resistor, use multiple vias to keep the trace potentials between the two conductors the same. vias are hi ghly resistive compared to a copper trace. multiple vias should be employed to lower the voltage drop due to current flowing through resistive vias. figure 49 illustrates a layout technique for a multiple layered trace sense resistor. figure 48. illustrates a layout example of a current sense resistor made from a pcb trace current flow in current flow out sense neg(-) sense pos(+) the length of the trace between the two sense lines defines the sense resistor value. top bottom trace trace via via trace via (a) cross section view (b) topview pcb pcb
isl28022 30 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8386.7 october 2, 2015 for additional products, see www.intersil.com/en/products.html submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o the web to make sure that you have the latest revision. date revision change october 2, 2015 fn8386.7 changed in table 15 on page 16, bit d0 from ?fs0? to ?0?. added statement in number 3 (second to the last sent ence of ?calibration register 05h (read/write)? on page 17, which reads ?the calibration value...? june 17, 2015 fn8386.6 added related literature section on page 1. added dpm portfolio comparison table on page 5. removed typical applications section and ma de into an application note (an1955). february 20, 2015 fn8386.5 electrical specifications table on page 7- dc accuracy under test conditions: updated vsense from 300m v to 320mv. table 5 on page 14: changed in range (mv) column from 300 to 320. table 8 on page 16 updated ?full-scale in title from 300mv to 320mv. equation 1 on page 17: changed n=0 to n=2. calibration register 05h (read/write) section on page 17 above equation 2, changed range: (300mv, 160mv, 80mv and 40mv) to (320mv, 160mv, 80mv and 40mv). over-ranging section on page 24: updated maximum set range from (300mv) to (320mv). table 22 on page 24 changed pg11 from 300mv to 320mv. point of load power monitor section on page 29: changed shunt voltage from 300mv to 320mv. equation 22 on page 28: changed value from 0.30 to 0.32. page 31 updated v shunt range from 300mv to 320mv. june 9, 2014 fn8386.4 equation 17 on page 26 added i l before = r dcr figure 42 on page 27 changed ?of a strip? to ?for a strip? figure 47 on page 28 changed ?current flow? to ?a current flow? last sentence in paragraph following figure 46 on page 28 and second sentence in paragraph under equation 28 on page 32 changed ?10 7 ? to ?10 -7 ? april 17, 2014 fn8386.3 text revi sions done in section ? signal integrity ? on page 23 . added section ? lossless current sensing (dcr) ? on page 26 and ?monitoring multicell battery levels using the isl28022 broadcast command? on page 36. updated the ordering information on page 3 by removing r-spec parts. october 10, 2013 fn8386.2 add ed sections from ? shunt resistor selection ? on page 25 to ?an efficiency measurement using the isl28022 broadcast feature? on page 35. april 26, 2013 fn8386.1 added r-spec parts to ordering information and updated verbiage in about intersil. april 16, 2013 fn8386.0 initial release
isl28022 31 fn8386.7 october 2, 2015 submit document feedback package outline drawing m10.118 10 lead mini small outline plastic package rev 1, 4/12 detail "x" side view 2 typical recommended land pattern top view pin# 1 id 0.18 - 0.27 detail "x" 0.10 0.05 (4.40) (3.00) (5.80) h c 1.10 max 0.09 - 0.20 33 gauge plane 0.25 0.95 ref 0.55 0.15 b 0.08 c a-b d 3.00.05 12 10 0.85010 seating plane a 0.50 bsc 3.00.05 4.90.15 (0.29) (1.40) (0.50) d 5 5 side view 1 dimensioning and tolerancing conform to jedec mo-187-ba plastic interlead protrusions of 0.15mm max per side are not dimensions in ( ) are for reference only. dimensions are measured at datum plane "h". plastic or metal protrusions of 0.15mm max per side are not dimensions are in millimeters. 3. 4. 5. 6. notes: 1. 2. and amsey14.5m-1994. included. included. 0.10 c m
isl28022 32 fn8386.7 october 2, 2015 submit document feedback package outline drawing l16.3x3b 16 lead quad flat no-lead plastic package rev 1, 4/07 located within the zone indicate d. the pin #1 indentifier may b e unless otherwise specified, t olerance : decimal 0.05 tiebar shown (if present) i s a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing c onform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" typical recomme nded land pattern top view bottom view side view 9 ( 2. 80 typ ) ( 1. 70 ) (4x) 0.15 ( 12x 0 . 5 ) ( 16x 0 . 60) ( 16x 0 . 23 ) 0 . 90 0.1 index area pin 1 6 a 3.00 b 3.00 12 4 4 5 8 16x 0.40 0.10 5 0 . 2 ref c 0 . 00 min. 0 . 05 max. b c ma 0.10 c - 0.05 base plane 0.10 c see detail "x" c 0.08 seating plane + 0.07 16x 0.23 16 13 12x 1.5 4x 0.50 1 6 pin #1 index area 1 .70 + 0.10 - 0.15

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